Post by breckjensen on Nov 29, 2017 2:58:08 GMT -5
hello,
Is there a way to measure time on the FPGA fabric in between triggering events? For example, I would like to measure the time in clock cycles of the AXI bursts of my design. RTL simulation does not allow me to run real-size benchmarks.
Ideally, there should be an IP that can be triggered by start/stop events/signals and expose the time through an AXI4-lite interface. I am using the ILA, but its timeline is not in clock cycles/ns/ps etc.
Please help.
Thanks!
I didn't find the right solution from the Internet.
References:
forums.xilinx.com/t5/General-Technical-Discussion/Measuring-time-of-AXI-bursts/td-p/809457
commercial product animation
Is there a way to measure time on the FPGA fabric in between triggering events? For example, I would like to measure the time in clock cycles of the AXI bursts of my design. RTL simulation does not allow me to run real-size benchmarks.
Ideally, there should be an IP that can be triggered by start/stop events/signals and expose the time through an AXI4-lite interface. I am using the ILA, but its timeline is not in clock cycles/ns/ps etc.
Please help.
Thanks!
I didn't find the right solution from the Internet.
References:
forums.xilinx.com/t5/General-Technical-Discussion/Measuring-time-of-AXI-bursts/td-p/809457
commercial product animation